Micrel, Inc.

MICRF230

Ordering Information

Part Number

Top Marking

Junction

Temperature Range

Package

MICRF230YQS

MICRF230YQS

–40°C to +105°C

16-Pin 4.9mm × 6.0mm QSOP

Pin Configuration

16-Pin 4.9mm × 6.0mm QSOP (QS)

(Top View)

Pin Description

Pin

Number

Pin

Name

Type

Pin Function

1

RO1

Input

Reference resonator connection (to the Pierce oscillator). Can also be driven by external

GND during normal operation.

2

RFGND

Supply

Ground connection for ANT RF input. Connect to PCB ground plane.

3

ANT

Input

Antenna input. RF signal input from antenna. Internally AC coupled. It is recommended to use

a matching network with an inductor to RF ground to improve ESD protection.

4

RFGND

Supply

Ground connection for ANT RF input. Connect to PCB ground plane.

5

CDEC

Supply

Internal supply decoupling access. Bypass to PCB ground plane with a 0.1µF ceramic

capacitor located as close to pin as possible. Maximum operating voltage is 3.6V.

6

SQ

Input

Squelch control logic-level input. An internal pull-

up (3μA typical) pulls the logic-input HIGH

when the device is enabled. A logic LOW on SQ squelches, or reduces, the random activity

on DO pin when there is no RF input signal.

7

VDD

Supply

Positive supply connection (for all chip functions). Bypass with 1µF capacitor located as close

to the VDD pin as possible.

8

EN

Input

Enable control logic-level input. A logic-level HIGH enable the device. A logic-level LOW put

the device to shutdown mode. An internal pull-down (3µA typical) pulls the logic input LOW.

The device is designed to start up in shutdown state. The EN pin should be kept at logic low

(shutdown state) until after the supply voltage on VDD is stabilized. If the application is

designed to have the EN pin always pulled high, it is recommended to add a shunt capacitor of

0.47µF from the EN pin to ground.

9

GND

Supply

Ground connection for all chip functions except for RF input. Connect to PCB ground plane.

April 15, 2015

2

Revision 2.0