TC654 datasheet(15/38 Pages) MICROCHIP

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DS20001734C-page 15

TC654/TC655

5.0

SERIAL COMMUNICATION

5.1

SMBus 2-Wire Interface

The Serial Clock Input (SCLK) and the bi-directional

data port (SDA) form a 2-wire bi-directional serial port

for communicating with the TC654/TC655. The follow-

ing bus protocols have been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following Serial Bus conventions have

been defined.

TABLE 5-1:

TC654/TC655 SERIAL BUS

CONVENTIONS

5.1.1

DATA TRANSFER

The TC654/TC655 support a bi-directional 2-Wire bus

and data transmission protocol. The serial protocol

sequencing is illustrated in Figure 1-1. Data transfers

are initiated by a Start condition (Start), followed by a

device address byte and one or more data bytes. The

device address byte includes a Read/Write selection

bit. Each access must be terminated by a Stop Condi-

tion (Stop). A convention call Acknowledge (ACK) con-

firms the receipt of each byte. Note that SDA can only

change during periods when SCLK is low (SDA

changes while SCLK is high are reserved for Start and

Stop conditions). All bytes are transferred MSB (most

significant bit) first.

5.1.2

MASTER/SLAVE

The device that sends data onto the bus is the transmit-

ter and the device receiving data is the receiver. The

bus is controlled by a master device which generates

the serial clock (SCLK), controls the bus access and

generates the Start and Stop conditions. The TC654/

TC655 always work as a slave device. Both master and

slave devices can operate as either transmitter or

receiver, but the master device determines which mode

is activated.

5.1.3

START CONDITION (START)

A high-to-low transition of the SDA line while the clock

(SCLK) is high determines a Start condition. All com-

mands must be preceded by a Start condition.

5.1.4

ADDRESS BYTE

Immediately following the Start Condition, the host

must transmit the address byte to the TC654/TC655.

The 7-bit SMBus address for the TC654/TC655 is

0011 011

. The 7-bit address transmitted in the serial

bit stream must match for the TC654/TC655 to respond

with an Acknowledge (indicating the TC654/TC655 is

on the bus and ready to accept data). The eighth bit in

the Address Byte is a Read-Write Bit. This bit is a ‘1’ for

a read operation or ‘0’ for a write operation. During the

first phase of any transfer, this bit will be set = 0 to indi-

cate that the command byte is being written.

5.1.5

STOP CONDITION (STOP)

A low-to-high transition of the SDA line while the clock

(SCLK) is high determines a Stop condition. All opera-

tions must be ended with a Stop condition.

5.1.6

DATA VALID

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data. Each data transfer is initiated with a Start

condition and terminated with a Stop condition. The

number of the data bytes transferred between the Start

and Stop conditions is determined by the master device

and is unlimited.

Term

Description

Transmitter

The device sending data to the bus.

Receiver

The device receiving data from the

bus.

Master

The device which controls the bus: ini-

tiating transfers (Start), generating the

clock and terminating transfers (Stop).

Slave

The device addressed by the master.

Start

A unique condition signaling the

beginning of a transfer indicated by

SDA falling (High to Low) while SCLK

is high.

Stop

A unique condition signaling the end

of a transfer indicated by SDA rising

(Low to High) while SCLK is high.

ACK

A Receiver acknowledges the receipt

of each byte with this unique condi-

tion. The Receiver pulls SDA low

during SCLK high of the ACK clock-

pulse. The Master provides the clock

pulse for the ACK cycle.

Busy

Communication is not possible

because the bus is in use.

NOT Busy

When the bus is idle, both SDA and

SCLK will remain high.

Data Valid

The state of SDA must remain stable

during the high period of SCLK in

order for a data bit to be considered

valid. SDA only changes state while

SCLK is low during normal data trans-

fers. (See Start and Stop conditions)

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