HV7321 datasheet(13/30 Pages) MICROCHIP

13 / 30 page

 2016 Microchip Technology Inc.

DS20005639A-page 13

HV7321

1.1

TYPICAL TIMING DIAGRAMS

Figure 1-1 shows the timing of control inputs and RTZ,

T/R and RXDMP switches per each channel of the

HV7321.

Upon the completion of a receiving period, an RTZ

period (SEL, NEG, POS = 000) should be asserted

before transmitting again.

FIGURE 1-1:

Logic Input Timing Diagram.

FIGURE 1-2:

TX Output Timing Diagram.

FIGURE 1-3:

Timing Diagram of HV7321 TX Output and Switches in CW Mode-1 Driven by

External CW Source.

001

010

000

010

001

101

110

100

110

101

tdr1

tr1

tf2

tdf2

tr3

tdr3

tf1

tdf1

tr2

tdr2

tf3

tdf3

tdr4

tr4

tf5

tdf5

tr6

tdr6

tf4

tdf4

tr5

tdr5

tf6

tdf6

output

SEL input

NEG input

POS input

TX output

VPP0

SEL input

NEG input

POS input

RTZSW switch

tRTZSW(OFF)

RX time

PWS input

tMC

CW-mode

TRSW switch

RXDMP switch

RTZ+

B-Mode

OFF

RTZ

TX time

OFF

VNN0

RTZ

VPP1

VNN1

RTZ

RTZ+

000

011

001

010

101

110

OFF

tTRSW(OFF)

tRXDMP(ON)

tRTZSW(ON)

tTRSW(ON)

tRXDMP(OFF)

RX time

External CW Source

VCW+

External CW source

SEL Input

NEG Input

POS Input

MODE

Input

External CW Source

VCW-

HV7321

Tx Output

RTZ

Hi-Z

Per Ch CW

Delay in external CW source

RTZ

CW end

MODE = 0

MODE = 1

000

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