GC2011A datasheet(13/50 Pages) TI

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Texas Instruments Incorporated

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GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

symmetric filter modes. The feedback circuit will also negate the reverse data, if desired, to implement anti-symmetric

filters. In non-symmetric modes the feedback samples are cleared.

There are four filter coefficients stored within each filter cell. The C-Sel signal is a two bit control which selects

which coefficient to use at what time. The C-Sel signal can be forced to any value, it can toggle between two coefficients,

or can rotate through all four coefficients. The C-Sel signal is synchronized to the LSBs of the control counter when

toggling between coefficients.

In the cascade mode the A and B paths are used in series as a single path with 32 filter cells. In this mode the

data-out and sum-out outputs of path A are fed into the data-in and sum-in inputs of path B, and the feedback-out of

path B is fed into the feedback-in of path A.

The two paths are independent and can be programmed differently, for example path A can be interpolating

while path B is decimating.

2.7

FILTER CELL

A block diagram of the filter cell is shown in Figure 5.

Figure 5. The Filter Cell

The 12 bit forward and reverse data samples are delayed and then passed to the 12 bit adder. The amount of

delay depends upon the selected filtering modes. In the normal mode the samples are delayed by one clock. In the

decimate by 2 mode the samples are delayed two cycles and in the decimate by four mode the forward samples are

Rev

Out

Data

C-Sel

Coefficient

I/O

Sum

Out

C-Sel

Out

Data

Out

Rev

Z-(1,2,4)

Unsigned Mode

Forward Delay Control

Reverse Delay Control

NOTE: The delay circuits can also hold the data

during interpolation.

12 Bits

2 Bits

16 Bits

32 Bits

14 Bits

28 Bits

14 LSBs

32 Bits

12 Bit Signed

14 by 14 Bit Multiplier

32 Bit Adder

or unsigned Adder

CIN

Z-(1,2,4)

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