GL603USB datasheet(18/41 Pages) ETC

18 / 41 page

09/22/00

GL603USB/GL603USB-A/GL603USB-B

Revision 1.4

0: Bank 0 (00h-7Fh)

ZO: Zero bit

1: The result of an arithmetic or logic operation is zero

0: The result of an arithmetic or logic operation is not zero

HC: Half Carry/Borrow bit

1: Carry or not borrow from the 4

th low order bit

0: Borrow or not carry from the 4

th low order bit

CA: Carry/Borrow bit

1: Carry or not borrow from the most significant bit

0: Borrow or not carry from the most significant bit

Value on POR: “- - 0 - - 0 0 0”

INDAR: (Address 04h/84h, Indirect address register)

R/W

INDAR7

INDAR6

INDAR5

INDAR4

INDAR3

INDAR2

INDAR1

INDAR0

Any instruction using the INDF register actually accesses the register pointed by the INDAR register.

Value on POR: “x x x x x x x x”

[1]

Note 1: “x” means unknown

PORT1 (Address 06h, Port 1 data register)

R/W

PORT1.6

PORT1.5

PORT1.4

PORT1.3

PORT1.2

PORT1.1

PORT1.0

PORT1 is a 7-bits latch for Port 1.0~Port 1.6. Reading the PORT1 register gets the status of the pins.

Writing to it will write to the port latch. All write operations are read-modify-write operations.

PORT1CON is used to enable/disable every bits of the port latch.

Port 1.5 and Port 1.6 are combined with USB D+ and D- pins and can be used only when USBPS2 bit at

MODSEL is cleared. These 2 I/O pins are open drain output and should be external pulled up at PS/2 mode.

Value on POR: “- x x x x x x x”

PORT2 (Address 07h, Port 2 data register)

R/W

PORT2.7

PORT2.6

PORT2.5

PORT2.4

PORT2.3

PORT2.2

PORT2.1

PORT2.0

PORT2 is an 8-bits latch for Port 2.0~Port 2.7. Reading the PORT2 register reads the status of the pins.

Writing to it will write to the port latch. All write operations are read-modify-write operations.

PORT2CON is used to enable/disable every bits of the port latch.

Value on POR: “x x x x x x x x”

PCHBUF (Address 0Ah/8Ah, Write buffer of Program Counter’s bit 11-8)

R/W

PCHBUF3

PCHBUF2

PCHBUF1

PCHBUF0

Write buffer for upper 4-bit of Program Counter. The upper byte of Program Counter is not directly

accessible. PCHBUF is a holding register for the PC[11:8] that are transferred to the upper byte of the

Program Counter when branch occur. Please see PCL register to get more detail information.

Value on POR: “- - - - 0 0 0 0”

INTEN (Address 0Bh/8Bh, Interrupt enable register)

R/W

GIE

TMROEN

TMROF

GIE: Global interrupt enable bit

1: Enable all interrupts

0: Disable all interrupts

TMROEN: Timer overflow interrupt enable bit

1: Enable timer interrupt

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