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CY28158
Document #: 38-07039 Rev. *B
Page 3 of 10
Function Table[2]
SEL133
/100#SEL1SEL0
CPU
(MHz)
3V66
(MHz)
PCI
(MHz)
48MHZ
(MHz)
REF
(MHz)
IOAPIC
(MHz)
0
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
1
100.227[3]
66.818[3]
33.409[3]
48.008[3]
14.318[3]
16.705[3]
0
1
0
100
66.67
33.33
OFF
14.318
16.67
0
1
1
100
66.67
33.33
48.008[3]
14.318
16.67
1
0
0
TCLK/2
TCLK/4
TCLK/8
TCLK/2
TCLK
TCLK/16
1
0
1
N/A
N/A
N/A
N/A
N/A
N/A
1
1
0
133.33
66.67
33.33
OFF
14.318
16.67
1
1
1
133.33
66.67
33.33
48.008[3]
14.318
16.67
Actual Clock Frequency Values
Clock Output
Target
Frequency
(MHz)
Actual
Frequency
(MHz)
PPM
CPU
100.0
99.126
–8740
CPU
133.33
132.769
–4208
48MHZ
48.0
48.008
167
Clock Enable Configuration
CPU_STOP#
PWR_DWN#
PCI_STOP#
CPU
3V66
PCI
PCI_F
REF
IOAPIC
OSC.
VCOs
X
0
X
LOW
LOW
LOW
LOW
LOW
OFF
OFF
0
1
0
LOW
LOW
LOW
ON
ON
ON
ON
01
1
LOW
LOW
ON
ON
ON
ON
ON
1
1
0
ON
ON
LOW
ON
ON
ON
ON
1
1
1
ON
ONONON
ON
ON
ON
Clock Driver Impedances
Impedance
Buffer Name
VDD Range
Buffer Type
Minimum
Ω
Typical
Ω
Maximum
Ω
CPU, IOAPIC
2.375V – 2.625V
Type 1
13.5
29
45
48MHZ, REF
3.135V – 3.465V
Type 3
20
40
60
PCI, 3V66
3.135V – 3.465V
Type 5
12
30
55
Note:
2.
TCLK is a test clock driven in on the X1 input in test mode.
3.
This selection is defined as “N/A” or “Reserved.”
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