CS8416-CS datasheet(38/48 Pages) CIRRUS

38 / 48 page

CS8416

DS578PP2

11 PIN DESCRIPTION - HARDWARE MODE

821

RXP3

RXP2

RXP1

RXP0

RXN

VA+

AGND

FILT

RST

RXSEL1

RXSEL0

TXSEL1

TXSEL0

NV/RERR

OLRCK

OSCLK

SDOUT

OMCK

RMCK

VD+

DGND

VL+

RCBL

96 KHZ

AUDIO

RXP[3:0]

RXN

Additional AES3/SPDIF Receiver Port

(Input) - Single-ended receiver inputs carrying AES3 or

S/PDIF digital data. These inputs comprise the 4:2 S/PDIF Input Multiplexer. The select line control is

the RXSEL[1:0] pins. Please note that any unused inputs can be left floating. See Appendix A for rec-

ommended input circuits.

AES/SPDIF Input -

Used along with RXP[X] to form an AES3 differential input. In single-ended

operation this should be capacitively coupled to ground.

VD+

VA+

VL+

Positive Digital Power

–3.3 V

Positive Analog Power –

3.3 V

Positive Interface Power –

3.3V –5.0 V

DGND

AGND

Digital/Interface Ground

Analog Ground

RX_SEL0

RX_SEL1

Receiver_MUX Selector (Input)

- used to select which pin, RXP[3:0], is used for the receiver

input.

TX_SEL0

TX_SEL1

TX Pin MUX SELECTION(Input)

- used to select which pin, RXP[3:0], is used for the TX pin

output.

FILT

PLL Filter Pin –

A RC network should be connected from this pin to AGND. For best PLL jitter

performance, this pin should be returned directly to the AGND pin

RST

RESET(Input) –

active low input . Resets CS8416 to default state, configuration pins are read on the

rising edge of this pin

NV/RERR

Non-Validity Receiver Error/Receiver Error (output)

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