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CAM35C44 Arkusz danych(PDF) 13 Page - SMSC Corporation |
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CAM35C44 Arkusz danych(HTML) 13 Page - SMSC Corporation |
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13 / 50 page ![]() 13 MULTIHOST CPU INTERFACE The CAM35C44 multihost CPU interface is capable of supporting three bus configurations; including, 1) an ISA-style address and data bus, 2) a multiplexed address/data bus with ISA-style read/write commands like the example shown in (FIGURE 4, and 3) a multiplexed address/data bus with a read/write select and data strobe like the example shown in FIGURE 5. The CPU interface type as well as the type- specific multiplexing of the processor/host interface pins (TABLE 1) is controlled by the Host Interface Select pins. FIGURE 4 - NEC UPD781C1X READ CYCLE FIGURE 5 - HITACHI HD63P01M1 READ CYCLE ADDR15-ADDR8 ADDR7-ADDR0 Data In AB[15:8] AB[7:0] ADDR STB nRD nWR ADDR15-ADDR8 ADDR7-ADDR0 Data In AB[15:8] AB[7:0] ADDR STB R/nW DATA STB |
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