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STM8AL3136 Arkusz danych(PDF) 98 Page - STMicroelectronics |
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STM8AL3136 Arkusz danych(HTML) 98 Page - STMicroelectronics |
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98 / 124 page ![]() Electrical parameters STM8AL313x/4x/6x STM8AL3L4x/6x 98/124 DocID18474 Rev 7 9.3.13 12-bit DAC characteristics In the following table, data are guaranteed by design, not tested in production. Table 53. DAC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage - 1.8 - 3.6 V VREF+ Reference supply voltage - 1.8 - VDDA IVREF Current consumption on VREF+ supply VREF+ = 3.3 V, no load, middle code (0x800) - 130 220 µA VREF+ = 3.3 V, no load, worst code (0x000) - 220 350 IVDDA Current consumption on VDDA supply VDDA = 3.3 V, no load, middle code (0x800) - 210 320 VDDA = 3.3 V, no load, worst code (0x000) - 320 520 TA Temperature range - -40 - 125 °C RL Resistive load(1) (2) DACOUT buffer ON 5 - - k Ω RO Output impedance DACOUT buffer OFF - 8 10 CL Capacitive load(3) -- - 50 pF DAC_OUT DAC_OUT voltage(4) DACOUT buffer ON 0.2 - VDDA-0.2 V DACOUT buffer OFF 0 - VREF+ -1 LSB tsettling Settling time (full scale: for a 12- bit input code transition between the lowest and the highest input codes when DAC_OUT reaches the final value ±1LSB ) RL ≥5 kΩ, CL≤ 50 pF - 7 12 µs Update rate Max frequency for a correct DAC_OUT (@95%) change when small variation of the input code (from code i to i+1LSB). RL ≥ 5 kΩ, CL ≤50 pF - - 1 Msps tWAKEUP Wakeup time from OFF state. Input code between lowest and highest possible codes. RL ≥5 kΩ, CL≤50 pF - 9 15 µs PSRR+ Power supply rejection ratio (to VDDA) (static DC measurement ) RL≥ 5 kΩ, CL≤50 pF --60 -35 dB 1. Resistive load between DACOUT and GNDA 2. Output on PF0 (48-pin package only) 3. Capacitive load at DACOUT pin 4. It gives the output excursion of the DAC |
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