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STM32F071X8 Arkusz danych(PDF) 16 Page - STMicroelectronics |
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STM32F071X8 Arkusz danych(HTML) 16 Page - STMicroelectronics |
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16 / 122 page ![]() Functional overview STM32F071x8 STM32F071xB 16/122 DocID025451 Rev 5 back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Figure 2. Clock tree Several prescalers allow the application to configure the frequency of the AHB and the APB domains. The maximum frequency of the AHB and the APB domains is 48 MHz. |
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