STM32L475RG datasheet(50/193 Pages) STMICROELECTRONICS

50 / 193 page

Functional overview

STM32L475xx

50/193

DocID027692 Rev 2

•

Transmission

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Three transmit mailboxes

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Configurable transmit priority

•

Reception

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Two receive FIFOs with three stages

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14 Scalable filter banks

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Identifier list feature

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Configurable FIFO overrun

•

Time-triggered communication option

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Disable automatic retransmission mode

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16-bit free running timer

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Time Stamp sent in last two data bytes

•

Management

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Maskable interrupts

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Software-efficient mailbox mapping at a unique address space

3.32

Secure digital input/output and MultiMediaCards Interface

(SDMMC)

The card host interface (SDMMC) provides an interface between the APB peripheral bus

and MultiMediaCards (MMCs), SD memory cards and SDIO cards.

The SDMMC features include the following:

•

Full compliance with MultiMediaCard System Specification Version 4.2. Card support

for three different databus modes: 1-bit (default), 4-bit and 8-bit

•

Full compatibility with previous versions of MultiMediaCards (forward compatibility)

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Full compliance with SD Memory Card Specifications Version 2.0

•

Full compliance with SD I/O Card Specification Version 2.0: card support for two

different databus modes: 1-bit (default) and 4-bit

•

Data transfer up to 48 MHz for the 8 bit mode

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Data write and read with DMA capability

3.33

Universal serial bus on-the-go full-speed (OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated

transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and

with the OTG 2.0 specification. It has software-configurable endpoint setting and supports

suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that can be

provided by the internal multispeed oscillator (MSI) automatically trimmed by 32.768 kHz

external oscillator (LSE).This allows to use the USB device without external high speed

crystal (HSE).

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