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STM32F301C6 Arkusz danych(PDF) 97 Page - STMicroelectronics |
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STM32F301C6 Arkusz danych(HTML) 97 Page - STMicroelectronics |
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97 / 135 page ![]() DocID025146 Rev 6 97/135 STM32F301x6 STM32F301x8 Electrical characteristics 114 Note: Refer to RM0366 Reference Manual I2S Section for more details about the sampling frequency (Fs), fMCK, fCK, DCK values reflect only the digital peripheral behavior, source clock precision might slightly change the values DCK depends mainly on ODD bit value. Digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max (I2SDIV+ODD)/(2*I2SDIV+ODD) and Fs max supported for each mode/condition. tv(WS) WS valid time Master mode - 20 ns th(WS) WS hold time Master mode 2 - tsu(WS) WS setup time Slave mode 0 - th(WS) WS hold time Slave mode 4 - tsu(SD_MR) Data input setup time Master receiver 1 - tsu(SD_SR) Slave receiver 1 - th(SD_MR) Data input hold time Master receiver 8 - th(SD_SR) Slave receiver 2.5 - tv(SD_ST) Data output valid time Slave transmitter (after enable edge) - 50 tv(SD_MT) Master transmitter (after enable edge) -22 th(SD_ST) Data output hold time Slave transmitter (after enable edge) 8 - th(SD_MT) Master transmitter (after enable edge) 1- 1. Guaranteed by characterization results. 2. 256xFs maximum is 36 MHz (APB1 Maximum frequency) Table 63. I2S characteristics(1) (continued) Symbol Parameter Conditions Min Max Unit |
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