EM44CM0884LBA

Dec. 2014

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Mode Register Definition

Mode Register Set

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM which contains

addressing mode, burst length, /CAS latency, WR (write recovery), test mode, DLL reset and various vendor‟s

specific opinions.

The defaults value of the register is not defined, so the mode register must be written after power up for proper

DDR2 SDRAM operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE and BA0/1.

The state of the address pins A0-A12 in the same cycle as /CS, /RAS, /CAS, /WE and BA0/1 going low is

written in the mode register.

Two clock cycles are requested to complete the write operation in the mode register. The mode register

contents can be changed using the same command and clock cycle requirements during operating as long as

all banks are in the idle state.

The mode register is divided into various fields depending on functionality. The burst length uses A0-A2,

addressing mode uses A3, /CAS latency (read latency from column address) uses A4-A6. A7 is used for test

mode. A8 is used for DDR reset. A9 ~ A11 are used for write recovery time (WR), A7 must be set to low for

normal MRS operation. With address bit A12 two Power-

Down modes can be selected, a “standard mode” and

a “low-power” Power-Down mode.