IDT72V3653_16 datasheet(7/30 Pages) IDT

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IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH

BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36

DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION

TheICC(f)currentforthegraphinFigure1wastakenwhilesimultaneouslyreadingandwritingaFIFOontheIDT72V3653/72V3663/72V3673withCLKA

andCLKBsettofS. Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputsweredisconnected

tonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofIDT72V3653/72V3663/72V3673inputs

driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.

CALCULATING POWER DISSIPATION

With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:

PT = VCC x ICC(f) +

Σ(CL x VCC2 x fo)

where:

number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)

output capacitance load

switchingfrequencyofanoutput

Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)

3040

506070

⎯ Clock Frequency ⎯ MHz

fdata = 1/2 fS

TA = 25

°C

CL = 0 pF

4662 drw03

100

VCC = 3.3V

VCC = 3.6V

VCC = 3.0V

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