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UU97950G-P48-R Arkusz danych(PDF) 8 Page - Unisonic Technologies |
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UU97950G-P48-R Arkusz danych(HTML) 8 Page - Unisonic Technologies |
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8 / 14 page ![]() UU97950 Advance CMOS IC UNISONICTECHNOLOGIESCO.,LTD 8 of 14 www.unisonic.com.tw QW-R125-048.a DETAILED COMMAND DESCRIPTION D7 (MSB) is bit for command or data judgement Refer to Command and data transfer method. C: 0—Next byte is RAM write data 1---Next byte is command Address set (ADSET) D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) C 0 P5 P4 P3 P2 P1 P0 Address data is specified in P[5:0] The address range can be set as 000000~100010 When the specified address is out of range, the address will be set to “000000”. The Reset initialize condition of the DDRAM address is “000000” Command Register Addresses(read mode): P[5:0]=23h-----REG1 Register address for software reset condition and EVR setting P[5:0]=24h-----REG2 Register address for the other settings EVR Set (EVRSET) D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) C 1 0 P4 P3 P2 P1 P0 It is able to control 32-step electrical register (EVR). It is able to set V0 voltage level (the max level voltage of LCD driving voltage). Electrical volume resister (EVR) is set “00000” in reset initialize condition In “00000” condition, V0 voltage output VLCD voltage. It is prohibited to set EVR V0 voltage under 2.5V. |
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