P12C508 datasheet(11/84 Pages) MICROCHIP

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Advance Information

DS40139A-page 11

PIC12C5XX

4.0

MEMORY ORGANIZATION

PIC12C5XX memory is organized into program mem-

ory and data memory. For devices with more than 512

bytes of program memory, a paging scheme is used.

Program memory pages are accessed using one STA-

TUS register bit. For the PIC12C509 with a data mem-

ory register ﬁle of more than 32 registers, a banking

scheme is used. Data memory banks are accessed

using the File Select Register (FSR).

4.1

Program Memory Organization

The PIC12C508 and PIC12C509 each have a 12-bit

Program Counter (PC) capable of addressing a 2K x

12 program memory space.

Only the ﬁrst 512 x 12 (0000h-01FFh) for the

PIC12C508 and 1K x 12 (0000h-03FFh) for the

PIC12C509 are physically implemented. Refer to

Figure 4-1.

Accessing

location

above

these

boundaries will cause a wrap-around within the ﬁrst

512 x 12 space (PIC12C508) or 1K x 12 space

(PIC12C509). The reset vector is at 0000h. Location

01FFh (PIC12C508) or location 03FFh (PIC12C509)

contains the internal clock oscillator calibration value.

This value should never be overwritten.

FIGURE 4-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC12C5XX

CALL, RETLW

PC<11:0>

Stack Level 1

Stack Level 2

0000h

7FFh

01FFh

0200h

On-chip Program

Memory

Reset Vector (note 1)

Note 1: Address 0000h becomes the effec-

tive reset vector. Location 01FFh

(PIC12C508) or location 03FFh

(PIC12C509) contains the MOVLW

XX clock calibration value.

512 Word (PIC12C508)

1024 Word (PIC12C509)

03FFh

0400h

On-chip Program

Memory

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