ADA4941-1YRZ-R7 datasheet(17/24 Pages) AD

17 / 24 page

ADA4941-1

Data Sheet

Rev. D | Page 16 of 23

In this case, the linear output voltage is limited by A1. On the

low end, the output of A1 starts to saturate and show degraded

linearity when VOP approaches 200 mV. On the high end, the

input of A1 becomes saturated and exhibits degraded linearity

when VIN moves beyond 4 V (within 1 V of VCC). This limits

the linear differential output voltage in the circuit shown in

Figure 50 to about 7.6 V p-p.

1kΩ

665Ω

1.02kΩ

402Ω

500Ω

REF

+5V

VS+

VS–

OUT+

–

VOP

OUT–

–

VON

VIN

+2.5V

Figure 51. 5 V Supply, G = 5, Single-Ended-to-Differential Amplifier

Figure 51 shows a single 5 V supply connection for G = 5. The

RF and RG network sets the gain of A1 to 2.5, and the 2.5 V at

the REF input provides a centered 2.5 V output common-mode

voltage. The transfer function is then

VOP

− VON = 5(VIN) − 5 V

(8)

The output range limits of A1 and A2 limit the differential

output voltage of the circuit shown in Figure 51 to approximately

8.4 V p-p.

DC ERROR CALCULATIONS

1kΩ

RS–IN

IBP–A2

IBN–A2

VOS–A1

500Ω

REF

OUT+

–

VOP

OUT–

–

VON

VOS–A2

RS–REF

IBP–A1

IBN–A1

Figure 52. DC Error Sources

Figure 52 shows the major contributions to the dc output

voltage error. For each output, the total error voltage can be

calculated using familiar op amp concepts. Equation 9 expresses

the dc voltage error present at the VOP output.



_A1

_IN

_A1

VOP_error

)

(

)

)(

(





















(9)

When using data from the Specifications tables, it is often more

expedient to use input offset current in place of the individual

input bias currents when calculating errors. Input offset current

is defined as the magnitude of the difference between the two

input bias currents. Using this definition, each input bias

current can be expressed in terms of the average of the two

input bias currents, IB, and the input offset current, IOS, as

IBP, N

= IB ± IOS/2. DC errors are minimized when RS = RF || RG. In

this case, Equation 9 is reduced to



)

(

)

(

_A1

VOP_error





















Equation 10 expresses the dc voltage error present at the VON

output.

VON_error

= −(VOP_error) + 2[VOS_A2 −

(IBP_A2)(RS_REF + 500)] + 1000(IBN_A2)

(10)

The internal 500 Ω resistor is provided on-chip to minimize dc

errors due to the input offset current in A2. The minimum

error is achieved when RS_REF = 0 Ω. In this case, Equation 10

is reduced to

VON_error

−(VOP_error) + 2[VOS_A2] + (IOS)1000

(RS_REF = 0 Ω)

The differential output voltage error VO_error, dm, is the

difference between VOP_error and VON_error:

VO_error, dm

= VOP_error − VON_error

(11)

The output offset voltage of each amplifier in the ADA4941-1

also includes the effects of finite common-mode rejection ratio

(CMRR), power supply rejection ratio (PSRR), and dc open-

loop gain (AVOL).

VOL

VOUT

PSRR

CMRR

_nom





(12)

where:

VOS_nom is the nominal output offset voltage without including

the effects of CMRR, PSRR, and AVOL.

Δ indicates the change in conditions from nominal.

VCM is the input common-mode voltage (for A1, the voltage at

IN, and for A2, the voltage at REF).

VS is the power supply voltage.

VOUT is either op amp output.

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