LM7372IMAX datasheet(13/15 Pages) NSC

13 / 15 page

Application Notes (Continued)

divider network is eliminated and the bias resistors at the

non-inverting inputs are returned to ground, see

Figure 3

(the pin numbers in

Figure 3 are given for the LLP and PSOP

packages, those in

Figure 1 are for the SOIC package). With

a split supply, note that the ground plane and the heatsink

copper must be separate and are at different potentials, with

the heatsink (pin 4 of the LLPand PSOP, pins 6,1,8,9 &16 of

the SOIC) now at a negative potential (V

−).

In either configuration, the area under the input pins should

be kept clear of copper (Whether ground plane copper or

heatsink copper) to avoid parasitic coupling to the inputs.

The LM7372 is stable with non inverting closed loop gains as

low as +2. Typical of any voltage feedback operational am-

plifier, as the closed loop gain of the LM7372 is increased,

there is a corresponding reduction in the closed loop signal

bandwidth. For low distortion performance it is recom-

mended to keep the closed loop bandwidth at least 10X the

highest signal frequency. This is because there is less loop

gain (the difference between the open loop gain and the

closed loop gain) available at higher frequencies to reduce

harmonic distortion terms.

Printed Circuit Board Layout and Evaluation Boards:

Generally, a good high-frequency layout will keep power

supply and ground traces away from the inverting input and

output pins. Parasitic capacitance on these nodes to ground

will cause frequency response peaking and possible circuit

oscillations (see Application Note OA-15 for more informa-

tion). National Semiconductor suggests the following evalu-

ation boards as a guide for high frequency layout and as an

aid in device testing and characterization:

Device

Package

Evaluation

Board PN

LM7372MA

16-Pin SOIC

None

LM7372ILD

8-Pin LLP

CLC730114

LM7372MR

8-Pin PSOP

CLC730121

These free evaluation boards are shipped automatically

when a device sample request is placed with National Semi-

conductor.

The DAP (die attach paddle) on the LLP-8, and the PSOP

should be tied to V−. It should not be tied to ground. See

respective Evaluation Board documentation.

20004926

FIGURE 3. Split Supply Application (LLP)

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