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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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WM8737 Arkusz danych(PDF) 12 Page - Wolfson Microelectronics plc |
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WM8737 Arkusz danych(HTML) 12 Page - Wolfson Microelectronics plc |
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12 / 38 page  WM8737L Preliminary Technical Data w AI Rev 3.0 May 2004 12 Test Conditions DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns ADCLRC set-up time to BCLK rising edge tLRSU 10 ns ADCLRC hold time from BCLK rising edge tLRH 10 ns ADCDAT propagation delay from BCLK falling edge tDD 0 10 ns CONTROL INTERFACE TIMING – 3-WIRE MODE CSB SCLK SDIN t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS 40 ns SCLK pulse cycle time tSCY 80 ns SCLK pulse width low tSCL 40 ns SCLK pulse width high tSCH 40 ns SDIN to SCLK set-up time tDSU 10 ns SCLK to SDIN hold time tDHO 10 ns CSB pulse width low tCSL 10 ns CSB pulse width high tCSH 10 ns CSB rising to SCLK rising tCSS 10 ns Pulse width of spikes which will be suppressed tSP 0 5 ns CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 Figure 5 Control Interface Timing – 2-Wire Serial Control Mode |
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