WM8750LEFLSLASHR datasheet(12/56 Pages) WOLFSON

Numer części	WM8750LEFL/R

Szczegółowy opis	STEREO CODEC FOR PORTABLE AUDIO APPLICATIONS

PDF	56 Pages

Scroll/Zoom	100%

Producent	WOLFSON [Wolfson Microelectronics plc]

Strona internetowa	http://www.wolfsonmicro.com

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WM8750L

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PP Rev 1.77 May 2003

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

MCLK

MCLKL

MCLKH

MCLKY

Figure 1 System Clock Timing Requirements

Test Conditions

CLKDIV2=0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,

unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

TMCLKL

MCLK System clock pulse width low

TMCLKH

MCLK System clock cycle time

TMCLKY

MCLK duty cycle

TMCLKDS

60:40

40:60

Test Conditions

CLKDIV2=1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,

unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

TMCLKL

MCLK System clock pulse width low

TMCLKH

MCLK System clock cycle time

TMCLKY

AUDIO INTERFACE TIMING – MASTER MODE

BCLK

(Output)

ADCDAT

ADCLRC/

DACLRC

(Outputs)

DACDAT

DDA

DHT

DST

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

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