1

PS8589E

09/15/04

Features

• Maximumratedfrequency:140MHz

• Low cycle-to-cycle jitter

• Input to output delay, less than 150ps

• External feedback pin allows outputs to be synchronized

to the clock input

• 5V tolerant input*

• Test mode allows bypass of the PLL for system testing

purposes (e.g., IBIS measurements)

• Clock frequency multipliers ½x to 4x dependent on option

• Packaging (Pb-free and Green available):

-16-pin,150-milSOIC (W)

-16-pin173-milTSSOP (L)

Description

The PI6C2408 is a PLL-based, zero-delay buffer, with the ability

to distribute eight outputs of up to 140 MHz at 3.3 V. Two banks of

four outputs exist, and, depending on product option ordered, can

supply either reference frequency, prescaled half frequency, or

multiplied2xor4xinputclockfrequencies. ThePI6C2408familyhas

a power-sparing feature: when input SEL2 is 0, the component will

3-state one or both banks of outputs depending on the state of input

SEL1. A PLL bypass test mode also exists. This product line is

available in high-drive and industrial environment versions.

An external feedback pin is used to synchronize the outputs to the

input; the relationship between loading of this signal and the other

outputs determines the input-output delay.

The PI6C2408 is characterized for both commercial and industrial

operation.

Block Diagram

PinConfiguration

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Zero-Delay Clock Buffer

PI6C2408

* FB_IN and CLKIN must reference the same voltage thresh-

olds for the PLL to deliver zero delay skewing

PLL

Option (-3, -4)

CLKIN

FB_IN

SEL1

SEL2

Decode

Logic

Decode

Logic

OUTA1

OUTA2

OUTA3

OUTA4

OUTB2

OUTB3

OUTB4

OUTB1

PI6C2408 (-1, -1H, -2, -3, -4)

÷2

PLL

CLKIN

FB_IN

SEL2

SEL1

OUTA1

OUTA2

OUTA3

OUTA4

OUTB2

OUTB3

OUTB4

OUTB1

PI6C2408-6

MUX

÷2

÷2

Option (-2, -3)

MUX

MUX

1

2

3

VDD

4

GND

5

OUTA2

6

OUTB2

7

SEL1

8

OUTB1

FB_IN

OUTA3

VDD

OUTB4

OUTB3

SEL2

16

15

14

13

12

11

10

9

CLKIN

OUTA1

GND

OUTA4

16-Pin

W, L