THine Electronics, Inc.

Security E

THCV220_Rev.2.20_E

Copyright©2016 THine Electronics, Inc.

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Data Enable

Figure 2 is the conceptual diagram of the basic operation of the chipset. THCV219 in Figure 2 is an example of

V-by-One

® HS Transmitter.

There are some requirements for DE. Figure 3 shows the timing diagram of it.

R/G/B

CONT

V,HSYNC

CTL

1

DE

THCV220

THCV219

R/G/B

CONT

VSYNC

HSYNC

DE=1, R/G/B,CONT

DE=0, CTL

DE=1, V,HSYNC=Fixed

DE=0, V,HSYNC

0

CTL are particular assigned bit among R/G/B,CONT

that can carry arbitrary data during DE=0 period.

Figure 2. Conceptual diagram of the basic operation of the chipset

High

Low

High

Valid Data

Valid Data

Invalid

Invalid

DE

HSYNC

VSYNC

RGB

CONT

THCV219

Input*

Invalid

Valid Data

CLKIN

Low

Valid Data

Invalid

Invalid

Valid Data

Low

High

Invalid

Valid Data

(RF=H)

High

Low

High

Valid Data

Valid Data

Keep the last data

of DE=L period

DE

HSYNC

VSYNC

RGB

CONT

Valid Data

CLKOUT

Low

Valid Data

Valid Data

Low

High

Valid Data

(RF=H)

Keep the last data

of DE=L period

Keep the last data

of DE=L period

Particular assigned bit ‘CTL’ is transmitted expect the first

and last pixel of Blanking period. Ohters are Low fixed.

Keep the

last data

Keep the

last data

Keep the

last data

*Refer to the data sheet of THCV219 for input operation

THCV220

Output

Figure 3. Data and synchronizing signals transmission timing diagram

Table 1. DE requirement

symbol

Parameter

min.

typ.

max.

Unit

tDEH

DE=High Duration

2tRCP

sec

tDEL

DE=Low Duration

2tRCP

sec