WM8772 datasheet(34/70 Pages) WOLFSON

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WM8772EDS – 28 PIN SSOP

Production Data

PD Rev 4.1 October 2004

MASTER MODE LRC FREQUENCY SELECT

In Master mode the WM8772EDS generates LRC and BCLK. These clocks are derived from the

master clock and the ratio of MCLK to LRC is set by RATE.

BIT

LABEL

DEFAULT

DESCRIPTION

0001010

Interface Control

8:6

RATE [2:0]

010

Master Mode

MCLK:LRC Ratio Select:

000: 128fs (DAC only)

001: 192fs (DAC only)

010: 256fs

011: 384fs

100: 512fs

101: 768fs

ADC OVERSAMPLING RATE SELECT

For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the

ADC signal processing oversample rate to 64fs. The 64fs oversampling rate is only available in

modes were a 96KHz rate is supported, i.e. 256fs or 384fs. In all other modes the ADC will stay in a

128fs oversampling rate irrespective of what this bit is set to.

BIT

LABEL

DEFAULT

DESCRIPTION

0001011

ADC Oversampling Rate

ADCOSR

ADC Oversampling Rate Select:

0: 128x oversampling

1: 64x oversampling

ADC HIGHPASS FILTER DISABLE

The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled

using software control bit ADCHPD.

BIT

LABEL

DEFAULT

DESCRIPTION

0001100

ADC Control

ADCHPD

ADC Highpass Filter Disable:

0: Highpass filter enabled

1: Highpass filter disabled

MUTE PIN DECODE

The MUTE pin can either be used an output or an input. When used as an input the MUTE pins

action can controlled by setting the DZFM bit to select the corresponding DAC for applying the MUTE

to. As an output its meaning is selected by the DZFM control bits. By default selecting the MUTE to

represent if DAC1 has received more than 1024 midrail samples will cause the MUTE to be asserted

a softmute on DAC1. Disabling the decode block will cause any logical high on the MUTE pin to

apply a softmute to all DAC’s.

BIT

LABEL

DEFAULT

DESCRIPTION

0001100

ADC Control

MPD

MUTE Pin Decode Disable:

0: MUTE pin decode enable

1: MUTE pin decode disable

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