WM8759

Advanced Information

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AI Rev 3.0 September 2004

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The outputs of the 2 DACs are buffered out of the device by buffer amplifiers capable of driving

loads of either line level or headphone level impedance. The advanced multi-bit DAC used in

WM8759 produces far less out of band noise than single bit traditional sigma delta DACs, and so

in most applications where line level output is required, no post DAC filter is required. Typically an

AC coupling capacitor and a DC setting resistor to ground are the only components required on

the output of the chip.

CLOCKING SCHEMES

In a typical digital audio system there is only one central clock source producing a reference clock

to which all audio data processing is synchronised. This clock is often referred to as the audio

system’s Master Clock. The external master clock can be applied directly through the MCLK input

pin with no configuration necessary for sample rate selection.

Note that on the WM8759, MCLK is used to derive clocks for the DAC path. The DAC path

consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In

a system where there are a number of possible sources for the reference clock it is recommended

that the clock source with the lowest jitter be used to optimise the performance of the DAC.

The device can be powered down by stopping MCLK. In this state the power consumption is

substantially reduced.

DIGITAL AUDIO INTERFACE

Audio data is applied to the internal DAC filters via the Digital Audio Interface. Three interface

formats are supported:

•

Right Justified mode

•

I

•

DSP mode

All formats send the MSB first. The data format is selected with the FORMAT pin. When

FORMAT is LOW, right justified data format is selected and word lengths of 16-bits may be used.

When the FORMAT pin is HIGH, I

may be used. (If a word length shorter than 24-bits is used, the unused bits should be padded

with zeros). If LRCIN is 4 BCKINs or less duration, the DSP compatible format is selected. Early

and Late clock formats are supported, selected by the state of the FORMAT pin.

‘Packed’ mode (i.e. only 32 or 48 clocks per LRCIN period) operation is also supported in both I

(16-24 bits) and right justified formats, (16 bit). If a ‘packed’ format of 16-bit word length is applied

(16 BCKINS per LRCIN half period), the device auto-detects this mode and switches to 16-bit

data length.

I

The WM8759 supports word lengths of 16-24 bits in I

In I

multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used

as a timing reference to indicate the beginning or end of the data words.

In I

length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word

length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements

are met. In I

transition. LRCIN is low during the left samples and high during the right samples.