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LMF90 Arkusz danych(PDF) 12 Page - National Semiconductor (TI) |
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LMF90 Arkusz danych(HTML) 12 Page - National Semiconductor (TI) |
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12 / 22 page ![]() 20 Applications Information (Continued) 22 PROGRAMMING PINS The LMF90 has five control pins that are used to program the filter’s characteristics via a three-level logic scheme In dual-supply applications these inputs are tied to either V a V b or GND in order to select a particular set of characteris- tics For example the W input (pin 1) sets the filter’s pass- band width to 055 f0 026 f0 or 0127 f0 when the W input is connected to V a GND or V b respectively Applying V b and GND to the D input (pin 10) will set the notch depth to 40 dB or 30 dB respectively The R input (pin 2) is another three-level logic input and it sets the clock-to-center-frequency ratio to 33331 501 or 1001 for input voltages equal to V a GND or V b respec- tively Note that the clock frequency referred to here is the frequency at the CLK pin and at the frequency divider output (if used) This is different from the frequency at the divider’s input LD (pin 3) sets the frequency divider’s division factor to either 716 596 or 2 for input voltages equal to V a GND or V b respectively XLS (pin 7) enables and disables the crystal oscillator and clock divider When XLS is connected to the positive supply the oscillator and divider are enabled and CLK is the output of the divider and can drive the clock inputs of other LMF90s When XLS is connected to GND the oscillator and divider are disabled and the CLK pin be- comes a clock input for CMOS-level signals Connecting XLS to the negative supply disables the oscillator and divid- er and causes CLK to operate as a TTL-level clock input Using an external 3579545 MHz color television crystal with the internal oscillator and divider it is possible to build a power line frequency notch for 50 Hz or 60 Hz line frequen- cies or their second and third harmonics using the LMF90 A 60 Hz notch is shown in the Typical Application circuit on the first page of this data sheet Connecting LD to V a changes the notch frequency to 50 Hz Changing the clock- to-center-frequency ratio to 501 results in a second-har- monic notch and a 331 ratio causes the LMF90 to notch the third harmonic Table I illustrates 18 different combinations of filter band- width depth and clock-to-center-frequency ratio obtained by choosing the appropriate W D and R programming volt- ages 23 DIGITAL INPUTS AND OUTPUTS As mentioned above the CLK pin can serve as either an input or an output depending on the programming voltage on XLS When CLK is operating as a TTL input it will oper- ate properly in both dual-supply and single-supply applica- tions because it has two logic thresholdsone referred to V b and one referred to GND When operating as an output CLK swings rail-to-rail (CMOS logic levels) XTAL1 and XTAL2 are the input and output pins for the internal crystal oscillator When using the internal oscillator (XLS connected to V a ) the crystal is connected between these two pins When the internal oscillator is not used XTAL2 should be left open XTAL1 can be used as an input for an external CMOS-level clock signal swinging from V b to V a The frequency of the crystal or the external clock applied to XTAL1 will be divided by the internal frequency divider as determined by programming voltage on the LD pin 24 SAMPLED-DATA SYSTEM CONSIDERATIONS OUTPUT STEPS Because the LMF90 uses switched-capacitor techniques its performance differs in several ways from non-sampled (con- tinuous) circuits The analog signal at the input to the inter- nal bandpass filter (pin 12) is sampled during each clock cycle and since the output voltage can change only once every clock cycle the result is a discontinuous output signal The bandpass output takes the form of a series of voltage ‘‘steps’’ as shown in Figure 3 The steps are smaller when the clock frequency is much greater than the signal frequen- cy Switched-capacitor techniques are used to set the summing amplifier’s gain Its input and feedback ‘‘resistors’’ are actu- ally made from switches and capacitors Two sets of these ‘‘resistors’’ are alternated during each clock cycle Each time these gain-setting components are switched there will be no feedback connected to the op amp for a short period of time (about 50 ns) This generates very low-amplitude output signals at fCLK a fIN fCLK b fIN 2fCLK a fIN etc The amplitude of each of these intermodulation compo- nents will typically be at least 70 dB below the input signal amplitude and well beyond the spectrum of interest TABLE I Operation of LMF90 Programming Pins Values given are for nominal levels of attenuation RV b (fCLK f0 e 100) GND (fCLK f0 e 50) V a (fCLK f0 e 3333) DW Amin BWf0 SBWf0 Amin BWf0 SBWf0 Amin BWf0 SBWf0 (dB) (dB) (dB) V b b 30 012 0019 b 30 012 0019 b 30 012 0019 V b GND b 30 026 0040 b 30 026 0040 b 30 026 0040 V a b 30 055 0082 b 30 055 0082 b 30 055 0082 V b b 35 012 0010 b 35 012 0010 b 35 012 0010 GND GND b 40 026 0024 b 40 026 0024 b 40 026 0024 V a b 40 055 0050 b 40 055 0050 b 40 055 0050 12 |
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