YMF721 datasheet(6/41 Pages) LSI

6 / 41 page

YMF721

July 10, 1997

- 6 -

FUNCTIONS

1. 1. Example of system configuration

1-1. System with MPU401 UART

This section describes two examples of systems that have an MPU401 UART in them.

In these examples, YMF701B, 711 or 715 (OPL3-SA, SA2 or SA3) has a built-in MPU401 UART.

(1) ISA BUS Connect System

Note :

YMF721 (OPL4-ML2) has MPU401 UART in it. Thus, for the above case, TXD of YMF7xx (OPL3-SAx)

is connected with RXD of YMF721 (OPL4-ML2) and MPU401 port (/MPUCS) of YMF721 (OPL4-ML2)

is disabled so that YMF7xx(OPL3-SAx) sends MIDI data directly to YMF721 (OPL4-ML2).

For the above case, FM synthesizer of YMF7xx (OPL3-SAx) is disabled and the one in YMF721 (OPL4-

ML2) is made active. (This control is made through /EXTEN pin of YMF7xx.) For the above system, the

data bus that connects with YMF721(OPL4-ML2) gains access to FM-synthesizer/Command/Control port

of YMF721(OPL4-ML2). (Chip select signal is outputted from /SYNCS pin of YMF7xx.)

For the source of master clock to be inputted to XI pin of YMF721 (OPL4-ML2), it is recommended to use

CLKO pin of YMF7xx (OPL3-SAx). For other methods, a crystal oscillator can be used by attaching it to

XI and XO pins of YMF721 (OPL4-ML), or a clock of 33.8688 MHz supplied from the system can be used.

When serial data outputs of YMF721 (OPL4-ML2), BCO, LRO and DO2 pins, are connected with external

serial data interface (BCLK_ML, LRCK_ML, SIN_ML) of YMF7xx (OPL3-SAx), the serial data is

converted to analog signal in YMF7xx (OPL3-SAx) and outputted as analog signal.

YMF7xx

(OPL3-SAx)

IOCHRDY

SA2-0

RESETDRV

/IOW

/IOR

SD7-0

TXD

LRCK_ML

BCLK_ML

SIN_ML

CLKO

/SYNCS

/EXTEN

ARDY

RST

A2-0

/IOW

/IOR

ADB7-0

ABDIR

/OPLCS

/MPUCS

FSP

RXD

BCO

LRO

DO2

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