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TMS55166 Arkusz danych(PDF) 38 Page - Texas Instruments

Numer części TMS55166
Szczegółowy opis  262144 BY 16-BIT MULTIPORT VIDEO RAM
PDF  70 Pages
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Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
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TMS55166 Arkusz danych(HTML) 38 Page - Texas Instruments

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TMS55165, TMS55166, TMS55175, TMS55176
262144 BY 16-BIT MULTIPORT VIDEO RAM
SMVS463 – DECEMBER 1995
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
ALT.
’551xx -60
’551xx - 70
UNIT
SYMBOL
MIN
MAX
MIN
MAX
UNIT
td(GHQSF)
Delay time, TRG high to QSF switching, full-register transfer
(see Note 16)
tTQD
25
25
ns
td(GLRH)
Delay time, TRG low to RAS high
tROH
10
15
ns
td(GLZ)
Delay time, TRG low to DQ in the low-impedance state
tOELZ
3
3
ns
td(MSRL)
Delay time, last SC high at boundary (127 or 255) to RAS low,
split-register transfer
15
20
ns
td(RHCL)
Delay time, RAS high to CAS low, CBR refresh
tRPC
0
0
ns
td(RHMS)
Delay time, RAS high to last SC high at boundary (127 or 255),
split-register-transfer
15
20
ns
td(RLCA)
Delay time, RAS low to column address valid
tRAD
15
30
15
35
ns
’551x5
tCSH
60
70
ns
td(RLCH)
Delay time, RAS low to CAS high
’551x6
tCSH
53
60
ns
()
yg
CBR
tCHR
10
10
ns
td(RLCL)
Delay time, RAS low to CAS low (see Note 17)
tRCD
20
43
20
50
ns
td(RLQSF)
Delay time, RAS low to QSF switching, full-register transfer
(see Note 16)
tRQD
65
70
ns
td(RLSH)
Delay time, RAS low to first SC high after TRG high,
early-load full-register transfer
tRSD
65
70
ns
td(RLTH)
Delay time, RAS low to TRG high (see Note 18)
tRTH
50
55
ns
td(RLWL)
Delay time, RAS low to first WEx low, read-modify-write
tRWD
80
95
ns
td(SCQSF)
Delay time, last SC high at boundary (127 or 255) to QSF switching,
split-register transfer (see Note 16)
tSQD
20
25
ns
td(SCTR)
Delay time, SC high to TRG high, full-register transfer
tTSL
5
5
ns
td(THRH)
Delay time, TRG high to RAS high (see Note 18)
tTRD
– 10
– 10
ns
td(THRL)
Delay time, TRG high to RAS low (see Note 18)
tTRP
40
50
ns
td(THSC)
Delay time, TRG high to SC high (see Note 18)
tTSD
20
25
ns
trf(MA)
Refresh time interval, memory
tREF
8
8
ms
tt
Transition time
tT
3
50
3
50
ns
† Timing measurements are referenced to VIL max and VIH min.
NOTES: 16. Switching times for QSF output are measured with a load equivalent to 1 TTL load and 30 pF, and output reference level is
VOH / VOL = 2 V/0.8 V.
17. The maximum value is specified only to assure RAS access time.
18. Real-time-load and late-load full-register transfer



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