MF6 datasheet(18/20 Pages) NSC

18 / 20 page

2.0 Designing with the MF6 (Continued)

2.5 ALIASING CONSIDERATIONS

Aliasing effects have to be taken into consideration when in-

put signal frequencies exceed half the sampling rate. For the

MF6 this equals half the clock frequency (f

CLK). When the in-

put signal contains a component at a frequency higher than

half the clock frequency, as in

Figure 19a, that component

will be “reflected” about f

CLK/2 into the frequency range be-

low f

CLK/2 as in Figure 19b. If this component is within the

passband of the filter and of large enough amplitude it can

cause problems. Therefore if frequency components in the

input signal exceed f

CLK/2 they must be attenuated before

being applied to the MF6 input. The necessary amount of at-

tenuation will vary depending on system requirements. In

critical applications the signal components above f

CLK/2 will

have to be attenuated at least to the filter’s residual noise

level. An example circuit is shown in

Figure 20 using one of

the uncommitted Op-Amps available in the MF6.

DS005065-30

fIN = 1.5 kHz (scope time base = 2 ms/div)

FIGURE 17. MF6-50 Abrupt Clock Frequency Change

DS005065-31

FIGURE 18. MF6-50 Step Input Response, Vertical =

2V/div., Horizontal = 1 ms/div., f

CLK = 100 kHz

DS005065-37

(a) Input Signal Spectrum

DS005065-38

(b) Output Signal Spectrum. Note that the input signal

at f

s/2 + f causes an output signal to appear at fs/2−f.

FIGURE 19. The phenomenon of aliasing in sampled-data systems. An input signal whose frequecy is greater than

one-half the sampling frequency will cause an output to appear at a frequency lower than one-half the sampling

frequency. In the MF6, f

sfCLK.

MF6 Arkusz danych(PDF) 18 Page - National Semiconductor (TI)

MF6 Arkusz danych(HTML) 18 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Arkusz danych Pobierz

Link URL