DocID027333 Rev 1

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HVLED001

Pin settings

27

GD

9

Gate driver output.

The output stage is able to drive the power MOSFET's and IGBT's gate.

VCC

10

Supply voltage of the IC.

Internal UVLO logic prevents the operation at voltages that are insufficient for an efficient gate

driving or signal processing.

Both a bulk capacitor (typically around 10 µF) and a high frequency filter capacitor (100 nF ceramic,

mounted as close as possible to the device) are connected between this pin and GND.

Internal clamp structure prevents accidental low energy spikes damaging the device.

Table 2. Pin description (continued)

Symbol Pin

Description