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STMPE321QTR Arkusz danych(PDF) 19 Page - STMicroelectronics |
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STMPE321QTR Arkusz danych(HTML) 19 Page - STMicroelectronics |
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19 / 40 page ![]() STMPE321 Interrupt controller module Doc ID 15791 Rev 3 19/40 INT_EN Interrupt enable register Address: 0x09 Type: R/W Reset: 0x01 Description: This register is used to enable the interruption from a system related interrupt source to the host. Writing ‘1’ in this register enables the corresponding interrupt event to generate interrupt signal at the INT pin. Note that even if the interrupt is not enabled, an interrupt event is still reflected in the interrupt status register. 76 543 2 1 0 GPIO RESERVED GEN FIFO POR [7] GPIO: One or more level transition in enabled GPIOs [6:3] RESERVED Must be set to ‘0’ at all times. [2] GEN: System INT (A2I, I2A, EOC) [1] FIFO: Data available in FIFO. This interrupt can be cleared only if FIFO is empty. [0] POR: Power-on reset |
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