PC97307 datasheet(3/218 Pages) NSC

3 / 218 page

Highlights

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— Software or hardware control

— 13 IRQ channel options

— Four 8-bit DMA channel options

— Demand mode DMA support

— An Enhanced Parallel Port (EPP) that is compatible

with the new version EPP 1.9, and is IEEE1284

compliant

— An Enhanced Parallel Port (EPP) that also supports

version EPP 1.7 of the Xircom speciﬁcation.

— Support for an Enhanced Parallel Port (EPP) as

mode 4 of the Extended Capabilities Port (ECP)

— An Extended Capabilities Port (ECP) that is IEEE

1284 compliant, including level 2

— Selection of internal pull-up or pull-down resistor for

Paper End (PE) pin

— Reduction of PCI bus utilization by supporting a de-

mand DMA mode mechanism and a DMA fairness

mechanism

— A protection circuit that prevents damage to the par-

allel port when a printer connected to it powers up or

is operated at high voltages

— Output buffers that can sink and source14 mA

s Three general purpose pins for three separate program-

mable chip select signals, as follows:

— Can be programmed for game port control

— The Chip Select 0 (CS0) signal produces open drain

output and is powered by the VCCH

— The Chip Select 1 (CS1) and 2 (CS2) signals have

push-pull buffers and are powered by the main VDD

— Decoding of chip select signals depends on the ad-

dress and the Address Enable (AEN) signals, and

can be qualiﬁed using the Read (RD) and Write

(WR) signals.

s 16 single-bit General Purpose I/O ports (GPIO):

— Modiﬁable addresses that are referenced by a 16-bit

programmable register

— Programmable direction for each signal (input or

output) with conﬁguration lock

— Programmable drive type for each output pin (open-

drain or push-pull) with conﬁguration lock

— Programmable option for internal pull-up resistor on

each input pin with conﬁguration lock

— A back-drive protection circuit

s An X-bus data buffer that connects the 8-bit X data bus

to the ISA data bus

s Clock source options:

— Source is a 32.768 KHz crystal - an internal frequen-

cy multiplier generates all the required internal fre-

quencies.

— Source may be either a 48 MHz or 24 MHz clock in-

put signal.

s Enhanced Power Management (PM), including:

— Special conﬁguration registers for power down

— WATCHDOG timer for power-saving strategies

— Reduced current leakage from pins

— Low-power CMOS technology

— Ability to shut off clocks to all modules

s General features include:

— All accesses to the SuperI/O chip activate a Zero

Wait State (ZWS) signal, except for accesses to the

Enhanced Parallel Port (EPP) and to conﬁguration

registers

— Access to all conﬁguration registers is through an In-

dex and a Data register, which can be relocated

within the ISA I/O address space

— 160-pin Plastic Quad Flatpack (PQFP) package

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