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A6984 Arkusz danych(PDF) 20 Page - STMicroelectronics |
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A6984 Arkusz danych(HTML) 20 Page - STMicroelectronics |
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20 / 47 page ![]() Device description A6984 20/47 DocID030396 Rev 1 Figure 12. Example to select RTON, CTON for VOUT = 5 V Figure 13. Example to select RTON, CTON for VOUT = 12 V 4.3 Optional virtual ESR network A standard COT loop requires a high ESR output capacitor to generate a proper PWM signal. The A6984 architecture naturally supports output ceramic capacitors with the negligible ESR generating an internal voltage ramp proportional to the inductor current to emulate a high ESR output capacitor for the proper PWM comparator operation. The control scheme is designed to guarantee the minimum signal for the PWM comparator cycle-by-cycle operation with controlled duty cycle jitter, that is a natural duty cycle dithering that helps to reduce the switching noise emission for EMC. If required, an optional external virtual ESR network (see Figure 14 can be designed to generate a higher signal for the PWM comparator operation and remove the duty cycle dithering. This network requires the external voltage divider to set the output voltage and supports the LNM and LCM device operation. |
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