L99DZ120 datasheet(69/162 Pages) STMICROELECTRONICS

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L99DZ120

Application information

161

4.6.1

Change watchdog timing

The watchdog trigger time is configured by setting WD_TIME_x (CR 2). Writing to these bits

is possible only using the first SPI command after setting WD_CONFIG_EN = 1 (Config

Reg). The WD_CONFIG_EN bit is reset to 0 automatically with the next SPI command.

4.7

Fail-safe mode

4.7.1

Temporary failures

The devices enter Fail-safe mode in case of:



Watchdog failure



V1 turn on failure

–

V1 short (V1 < V1fail for t > tV1short)



V1 failure (V1 < VRTxfalling for t > tV1FS)



Thermal Shutdown TSD2

The Fail Safe functionality is also available in V1_Standby mode. During V1_Standby mode

the Fail Safe mode is entered in the following cases:



V1 failure (V1 < VRTxfalling for t > tV1FS)



Watchdog failure (if watchdog still running due to IV1 > Icmp_fal)



Thermal Shutdown TSD2

In Fail Safe mode the devices return to a fail safe state. The Fail Safe condition is indicated

to the system in the Global Status Byte. The conditions during Fail Safe mode are:



All outputs beside LS1_FSO and LS2_FSO are turned off



All Control Registers are set to fail safe default values



Write operations to Control Registers are blocked until the Fail Safe condition is

cleared. The following bits are not WRITE protected:

–

TRIG (CR1<bit 0>, Config Register <bit 0>): watchdog trigger bit

–

V2_x (CR1<bit 4:5>): Voltage Regulator V2 control

–

CR2 (bit <8:23>): Timer1 and Timer2 settings

–

OUT_HS_x (CR5 <bit 0:3>): OUT_HS configuration

–

OUT15_x (CR6<bit 0:3>): OUT15 configuration

–

PWMx_freq_y (CR12): PWM frequency configuration

–

PWMx_DC_y (CR13 – CR17): PWM duty cycle configuration



LIN transmitter and SPI remain on (transmitters are deactivated in case of thermal

shutdown TSD1 (TSD1 cluster 5 or 6 in cluster mode)



Corresponding Failure Bits in Status Registers are set



FS Bit (Global Status Byte) is set



LS1_FSO and LS2_FSO will be turned on



Charge pump is switched off

If the Fail Safe mode was entered it keeps active until the Fail safe condition is removed and

the Fail Safe was read by SPI. Depending on the root cause of the Fail Safe operation, the

actions to exit Fail safe mode are as shown in the following table.

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