PC97338VLJ datasheet(6/221 Pages) NSC

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2.3.31 SIO Base Address Low Byte Register (SBAL), Index 4Ah .................................................... 63

2.3.32 SIO Base Address High Byte Register (SBAH), Index 4Bh .................................................. 63

2.3.33 System IRQ Input 1 Configuration Register (SIRQ1), Index 4Ch .......................................... 63

2.3.34 System IRQ Input 2 Configuration Register (SIRQ2), Index 4Dh .......................................... 64

2.3.35 System IRQ Input 3 Configuration Register (SIRQ3), Index 4Eh .......................................... 65

2.3.36 Plug-and-Play Configuration 3 Register (PNP3), Index 4Fh ................................................. 66

2.3.37 SuperI/O Configuration 3 Register (SCF3), Index 50h .......................................................... 67

2.3.38 Clock Control Register (CLK), Index 51h .............................................................................. 68

2.3.39 Manufacturing Test Register (MTEST), Index 52h ................................................................ 68

3.0 The Digital Floppy Disk Controller (FDC)

3.1 FDC FUNCTIONS ............................................................................................................................ 69

3.1.1 Microprocessor Interface ......................................................................................................... 69

3.1.2 System Operation Modes ........................................................................................................ 70

3.2 DATA TRANSFER ............................................................................................................................ 70

3.2.1 Data Rates .............................................................................................................................. 70

3.2.2 The Data Separator ................................................................................................................. 70

3.2.3 Perpendicular Recording Mode Support ................................................................................. 71

3.2.4 Data Rate Selection ................................................................................................................ 72

3.2.5 Write Precompensation ........................................................................................................... 72

3.2.6 FDC Low-Power Mode Logic .................................................................................................. 73

3.2.7 Reset ...................................................................................................................................... 73

3.3 THE REGISTERS OF THE FDC ...................................................................................................... 74

3.3.1 FDC Register Bitmaps ............................................................................................................. 74

3.3.2 Status Register A (SRA), Offset 000 .......................................................................................75

3.3.3 Status Register B (SRB), Offset 001 .......................................................................................76

3.3.4 Digital Output Register (DOR), Offset 010 .............................................................................. 77

3.3.5 Tape Drive Register (TDR), Offset 011 ................................................................................... 79

3.3.6 Main Status Register (MSR), Offset 100 ................................................................................. 80

3.3.7 Data Rate Select Register (DSR), Offset 100 ......................................................................... 82

3.3.8 Data Register (FIFO), Offset 101 ............................................................................................ 83

3.3.9 Digital Input Register (DIR), Offset 111 ................................................................................... 83

3.3.10 Configuration Control Register (CCR), Offset 111 ................................................................ 84

3.4 THE PHASES OF FDC COMMANDS .............................................................................................. 85

3.4.1 Command Phase .................................................................................................................... 85

3.4.2 Execution Phase ..................................................................................................................... 85

3.4.3 Result Phase ........................................................................................................................... 87

3.4.4 Idle Phase ............................................................................................................................... 88

3.4.5 Drive Polling Phase ................................................................................................................. 88

3.5 THE RESULT PHASE STATUS REGISTERS ................................................................................. 88

3.5.1 Result Phase Status Register 0 (ST0) .................................................................................... 88

3.5.2 Result Phase Status Register 1 (ST1) .................................................................................... 89

3.5.3 Result Phase Status Register 2 (ST2) .................................................................................... 90

3.5.4 Result Phase Status Register 3 (ST3) .................................................................................... 91

3.6 THE FDC COMMAND SET .............................................................................................................. 91

3.6.1 Abbreviations Used in FDC Commands .................................................................................. 92

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