Copyright 1998 National Semiconductor Corp.

6

www.national.com

NOTE: All digital outputs can sink/source 2 mA unless

otherwise specified. All digital inputs are Schmitt trig-

ger types. After reset all I/Os are set to input and all

pull-up or pull-down resistors are enabled. The p0[1]

will be pulled down at start-up.

ACSn

70

5

OUTPUT. Auxiliary Chip Select not. This signal becomes low if the address range

is within the programmed address range.

AD3..0

71-74

1b

OUTPUT. ADdress bit 3 to 0. In the HOLD mode these pins are input.

DAB7..0

82-75

1b

INPUT/OUTPUT (Slope controlled) Data bus bit 7..0

RCSn

83

5b

OUTPUT. ROM Chip Select not output. Low active if none of the internal peripher-

als or the ACSn is addressed.

AD10

84

1b

OUTPUT. Address bit 10. In the HOLD mode these pins are input.

RDn

85

1b

OUTPUT. Active low read. In the HOLD mode this pin is input.

AD11

86

1b

OUTPUT. Address bit 11. In the HOLD mode these pins are input.

AD9

87

1b

OUTPUT. Address bit 9. In the HOLD mode these pins are input.

AD8

88

1b

OUTPUT. Address bit 8. In the HOLD mode these pins are input.

AD13

89

1b

OUTPUT. Address bit 13. In the HOLD mode these pins are input

AD14

90

1b

OUTPUT. Address bit 14. In the HOLD mode these pins are input.

MI/AD17

91

5b

OUTPUT. Masked Interrupt output (HOLD mode only) or Address bit 17.

WRn

92

1b

OUTPUT. Active low write signal. In the HOLD mode this pin is input.

AD16,15, 12

93-95

1b

OUTPUT. Address bit 16,15 & 12. In the HOLD mode these pins are input.

AD7-4

96-99

1b

OUTPUT. Address bit 7 to 4. In the HOLD mode these pins are input.

CLKOUT

100

1b

OUTPUT. Fixed bit clock output (1.152Mhz). Synchronized to the DECT bit clock.

Will be logic ‘0’ if the DECT Dedicated Instruction Processor (DiP) is frozen or

reset.

Table 1:

Pin Description

PIN NAME

TYPE

DESCRIPTION