ST7FOXA0 datasheet(76/123 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7FOXA0

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9.3.6

Control/status register (ADCCSR)

Reset value: 0000 0000 (00h)

Bit 7 = EOC End of Conversion bit

This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH

0: Conversion is not complete

1: Conversion complete

Bit 6 = SPEED ADC clock selection bit

This bit is set and cleared by software. It is used together with the SLOW bit to

configure the ADC clock speed. Refer to the table in the SLOW bit description

(ADCDRL register).

Bit 5 = ADON A/D Converter on bit

This bit is set and cleared by software.

0: A/D converter is switched off

1: A/D converter is switched on

Bits 4:3 = Reserved, must be kept cleared.

Bits 2:0 = CH[2:0] Channel Selection

These bits select the analog input to convert. They are set and cleared by software.

Data register High (ADCDRH)

Reset value: xxxx xxxx (xxh)

EOC

SPEED

ADON

CH2

CH1

CH0

Read only

Read/write

Table 26.

Channel selection using CH[2:0]

Channel Pin(1)

The number of channels is device dependent. Refer to the device pinout description.

CH2

CH1

CH0

AIN0

AIN1

AIN2

AIN3

AIN4

Read only

Obsolete

Product(s)

- Obsolete

Product(s)

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