ST72344K2 datasheet(41/247 Pages) STMICROELECTRONICS

41 / 247 page

ST72344xx, ST2345xx

Supply, reset and clock management

Doc ID 12321 Rev 6

41/247

Supply, reset and clock management

The device includes a range of utility features for securing the application in critical

situations (for example in case of a power brown-out), and reducing the number of external

components.

7.1

Main features

●

Clock management

–

1 MHz high-accuracy internal RC oscillator (enabled by option byte)

–

1 to 16 MHz External crystal/ceramic resonator (enabled by option byte)

–

External Clock Input (enabled by option byte)

–

PLL for multiplying the frequency by 8 or 4 (enabled by option byte)

●

Reset sequence manager (RSM)

●

System integrity management (SI)

–

Main supply low voltage detection (LVD) with reset generation (enabled by option

byte)

–

Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main

supply (enabled by option byte)

Figure 13.

Clock, reset and supply block diagram

CR9

CR8

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

RCCRH/RCCRL Register

Tunable

RC Oscillator

DIVIDER

OSC

1-16 MHz

OSC Option bit

DIVIDER

PLL 1 MHz --> 8 MHz

PLL 1 MHz --> 4 MHz

External Clock (0.5-8 MHz)

RC Clock (1 MHz)

PLL Clock 8/4 MHz

OSC, PLLOFF

OSCRANGE[2:0]

Option bits

Crystal OSC (0.5-8 MHz)

PLLx4x8

OSC1

OSC2

fOSC2

MAIN CLOCK

CONTROLLER

WITH REAL-TIME

CLOCK(MCC/RTC)

fCPU

8 MHz

4 MHz

1 MHz

Option bit

DIVIDER*

DIV2EN

Option bit*

*not available if PLLx4 is enabled

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