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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ST72561AR7-Auto Arkusz danych(PDF) 30 Page - STMicroelectronics |
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ST72561AR7-Auto Arkusz danych(HTML) 30 Page - STMicroelectronics |
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30 / 324 page  Register and memory map ST72561-Auto 30/324 Doc ID 12370 Rev 8 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh LINSCI1 (LIN Master/Slave) SCI1ISR SCI1DR SCI1BRR SCI1CR1 SCI1CR2 SCI1CR3 SCI1ERPR SCI1ETPR SCI1 Status Register SCI1 Data Register SCI1 Baud Rate Register SCI1 Control Register 1 SCI1 Control Register 2 SCI1Control Register 3 SCI1 Extended Receive Prescaler Register SCI1 Extended Transmit Prescaler Register C0h xxh 00h xxh 00h 00h 00h 00h Read Only R/W R/W R/W R/W R/W R/W R/W 0050h Reserved Area (1 byte) 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 16-BIT TIMER T16CR2 T16CR1 T16CSR T16IC1HR T16IC1LR T16OC1HR T16OC1LR T16CHR T16CLR T16ACHR T16ACLR T16IC2HR T16IC2LR T16OC2HR T16OC2LR Timer Control Register 2 Timer Control Register 1 Timer Control/Status Register Timer Input Capture 1 High Register Timer Input Capture 1 Low Register Timer Output Compare 1 High Register Timer Output Compare 1 Low Register Timer Counter High Register Timer Counter Low Register Timer Alternate Counter High Register Timer Alternate Counter Low Register Timer Input Capture 2 High Register Timer Input Capture 2 Low Register Timer Output Compare 2 High Register Timer Output Compare 2 Low Register 00h 00h 00h xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h LINSCI2 (LIN Master) SCI2SR SCI2DR SCI2BRR SCI2CR1 SCI2CR2 SCI2CR3 SCI2ERPR SCI2ETPR SCI2 Status Register SCI2 Data Register SCI2 Baud Rate Register SCI2 Control Register 1 SCI2 Control Register 2 SCI2 Control Register 3 SCI2 Extended Receive Prescaler Register SCI2 Extended Transmit Prescaler Register C0h xxh 00h xxh 00h 00h 00h 00h Read Only R/W R/W R/W R/W R/W R/W R/W Table 4. Hardware register map (continued) Address Block Register label Register name Reset status Remarks(1) |
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