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Z86L02 Arkusz danych(PDF) 22 Page - Zilog, Inc.

Numer części Z86L02
Szczegółowy opis  Two On-Board Comparators
PDF  37 Pages
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Producent  ZILOG [Zilog, Inc.]
Strona internetowa  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z86L02 Arkusz danych(HTML) 22 Page - Zilog, Inc.

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Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8® Microcontrollers
Zilog
22
P R E L I M I N A R Y
DS96DZ80301
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The Z8 has five interrupts from four different
sources. These interrupts are maskable and prioritized
(Figure 16). The sources are divided as follows: the falling
edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge
of P32 (AN2), and one counter/timer. The Interrupt Mask
Register globally or individually enables or disables the
five interrupt requests (Table 5).
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All Z8 interrupts are
vectored through locations in program memory. When an
Interrupt machine cycle is activated, an Interrupt Request
is granted. This disables all subsequent interrupts, saves
the Program Counter and Status Flags, and then branches
to the program memory vector location reserved for that in-
terrupt. This memory location and the next byte contain the
16-bit starting address of the interrupt service routine for
that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs
are masked and the interrupt request register is polled to
determine which of the interrupt requests needs service.
User must select any Z86E08 mode in Zilog's C12 ICE-
BOX™ emulator. The rising edge interrupt is not directly
supported on the Z86CCP00ZEM emulator.
Figure 15. Counter/Timers Block Diagram
OSC
÷ 2
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
Clock
Logic
IRQ5
Internal Data Bus
Write
Write
Read
Internal Clock
Gated Clock
Triggered Clock
T
P31
External Clock
Internal
Clock
÷4
IN
*
Table 5. Interrupt Types, Sources, and Vectors
Vector
Name
Source
Location
Comments
IRQ0
AN2(P32)
0,1
External (F)Edge
IRQ1
REF(P33)
2,3
External (F)Edge
IRQ2
AN1(P31)
4,5
External (F)Edge
IRQ3
AN2(P32)
6,7
External (R)Edge
IRQ4
Reserved
8,9
Reserved
IRQ5
T1
10,11
Internal
Notes:
F = Falling edge triggered
R = Rising edge triggered



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