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DFE252012C Arkusz danych(PDF) 11 Page - MagnaChip Semiconductor. |
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DFE252012C Arkusz danych(HTML) 11 Page - MagnaChip Semiconductor. |
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11 / 17 page ![]() Confidential Datasheet Version 1.1 Mar. 2015. Revision 1.1 MagnaChip Semiconductor Ltd. 11 VIN ENP ENN UVLO VREG VREG power good VPOS VNEG Pull to GND(20ohm typ) Pull to GND (70ohm typ) Figure 20: Example of power off sequence activated Figure 21: Example of power off sequence activated by ENP and ENN when VIN is above UVLO by VIN falling below UVLO REGISTER MAP Slave Address : 3Eh [ Bit : 0111110x ] Table 1. I2C Registers Register R/W Function BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00h R/W VPOS Not Used VPOS[4] VPOS[3] VPOS[2] VPOS[1] VPOS[0] 01h R/W VNEG Not Used VNEG[4] VNEG[3] VNEG[2] VNEG[1] VNEG[0] 03h R/W DIS Not Used DISP DISN Table 2. VPOS/VNEG Voltage Setting NO. CODE HEX VPOS VNEG BIT4 BIT3 BIT2 BIT1 BIT0 1 0 0 0 0 0 00h 4.0V -4.0V 2 0 0 0 0 1 01h 4.1V -4.1V 3 0 0 0 1 0 02h 4.2V -4.2V 4 0 0 0 1 1 03h 4.3V -4.3V 5 0 0 1 0 0 04h 4.4V -4.4V 6 0 0 1 0 1 05h 4.5V -4.5V 7 0 0 1 1 0 06h 4.6V -4.6V 8 0 0 1 1 1 07h 4.7V -4.7V 9 0 1 0 0 0 08h 4.8V -4.8V 10 0 1 0 0 1 09h 4.9V -4.9V 11 0 1 0 1 0 0Ah 5.0V -5.0V VIN ENP ENN UVLO VREG VREG power good VPOS VNEG Pull to GND (20ohm typ) Pull to GND (70ohm typ) |
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