PC87415VCG datasheet(5/42 Pages) NSC

5 / 42 page

40 Pin Description (Continued)

42 IDE INTERFACE

Name

Type

Description

DD 150

DRIVE DATA BUS

The 16-bit bi-directional data bus to the drive The lower 8 bits are used for non data

8-bit transfers (eg registers ECC bytes)

DA 0

DRIVE ADDRESS LINE 0 OR TEST

The DA0 address line is asserted by the host to access a register or

data port in the drive It may also be used for testing during PCI Reset the rising edge of RST

samples

TEST

this pin If ‘‘low’’ all device output pins are forced to a TRI-STATE level

DA 1

DRIVE ADDRESS LINE 1 OR ENABLE

During normal operation the DA1 address line is asserted by the

host to access a register or data port in the drive During PCI Reset the rising edge of RST

samples this

ENABLE

pin and places its value in the Command Register bit-0

DA 2

DRIVE ADDRESS LINE 2 OR LEGACY

Dining normal operation the DA2 address line is asserted by the

host to access a register or data port in the drive During PCI Reset the rising edge of RST

samples this

LEGACY

pin and places its value in the Programming Interface Register bits 0 and 2

DIORDY

DRIVE IO CHANNEL READY

When the drive is not ready to respond to a data transfer request this

signal is negated (low) to extend the disk transfer cycle of any register access (read or write) When

DIORDY is not negated it remains in a high impedance state

DIOR

DRIVE IO READ

The read strobe signal for both channels The falling edge of DIOR

enables data from

a register or the data port of the drive onto the PCI-IDE chip

DIOW

DRIVE IO WRITE

The write strobe signal for both channels The rising edge of DIOW

clocks data from

the PCI-IDE chip into the register or the data port of the drive

DRST

DRIVE RESET

This signal from the PCI-IDE chip is asserted after power up or under software control (see

Control Register bits Table A) It is active for as long as the PCI Reset signal or if the reset bit in the

Control Register is set

CH1

CS1

CHANNEL 1 CHIP SELECT 1 AND 3

CH1

CS1

is the chip select signal to select the Command Block

Registers CH1

CS3

is the chip select signal to select the Control Block Registers

CH1

CS3

CH2

CS1

CHANNEL 2 CHIP SELECT 1 AND 3

CH2

CS1

is the chip select signal to select the Command Block

Registers CH2

CS3

is the chip select signal to select the Control Block Registers

CH2

CS3

CH1

INTRQ

DRIVE INTERRUPTS

These signals are used to interrupt the host system CH1

INTRQ is asserted only

when the drive(s) on channel 1 has a pending interrupt and the host has cleared nIEN in the drive’s

CH2

INTRQ

Device Control Register CH2

INTRQ is asserted only when the drive(s) on channel 2 has a pending

interrupt and the host has cleared nIEN in the Device Control Register

CH1

CHANNEL 1 DMA REQUEST

This signal is used when using the internal DMA controller When this

signal is asserted the selected drive on channel 1 is ready to transfer data

DMARQ

CH2

CHANNEL 2 DMA REQUEST

This signal is used when using the internal DMA controller When this

signal is asserted the selected drive on channel 2 is ready to transfer data

DMARQ

CH1

CHANNEL 1 DMA ACKNOWLEDGE

This signal is used when using the internal DMA controller When

asserted it signals the selected drive on channel 1 that data has been accepted or that data is available

DMACK

CH2

CHANNEL 2 DMA ACKNOWLEDGE

This signal is used when using the internal DMA controller When

asserted it signals the selected drive on channel 2 that data has been accepted or that data is available

DMACK

IRQ14

mirrors CH1

INT if Legacy mode is enabled

IRQ15

mirrors CH2

INT if Legacy mode is enabled

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