QL2009

3-36

The QL2009 is a 9,000 usable ASIC gate,16,000 usable PLD gate member of

the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination

of architecture, technology, and software tools to provide high speed, high

usable density, low price, and flexibility in the same devices. The flexibility

and speed make pASIC 2 devices an efficient and high performance silicon

solution for designs described using HDLs such as Verilog and VHDL, as well

as schematics.

The QL2009 contains 672 logic cells. With 225 maximum I/Os, the QL2009

is available in 144-pin TQFP, 208-PQFP, and 256-pin PBGA packages.

Software support for the complete pASIC families, including the QL2009, is

available through three basic packages. The turnkey QuickWorks

®

package

provides the most complete FPGA software solution from design entry to logic

synthesis (by Synplicity, Inc.), to place and route, to simulation.

The

QuickTools

who use Cadence, Mentor, Synopsys, Viewlogic, Veribest, or other third-party

tools for design entry, synthesis, or simulation.

Total of 225 I/O Pins

- 217 bidirectional input/output pins, PCI-compliant at 5.0V

in -1/-2 speed grades

- 4 high-drive input-only pins

- 4 high-drive input/distributed network pins

Four Low-Skew (less than 0.5ns) Distributed Networks

- Two array networks available to logic cell flip-flop clock, set, and

reset - each driven by an input-only pin

- Two global clock/control networks available to F1 logic input, and

logic cell flip-flop clock, set, reset; input and I/O register clock, reset,

enable; and output enable controls - each driven by an input-only pin, or

any input or I/O pin, or any logic cell output or I/O cell feedback

High Performance

- Input + logic cell + output delays under 6 ns

- Datapath speeds exceeding 225 MHz

- Counter speeds over 200 MHz

PRODUCT

SUMMARY

FEATURES