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L9660 Arkusz danych(PDF) 10 Page - STMicroelectronics |
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L9660 Arkusz danych(HTML) 10 Page - STMicroelectronics |
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10 / 49 page ![]() Electrical specifications L9660 10/49 DocID024714 Rev 2 2.4 Electrical characteristics 2.4.1 General 4.9 V V DD 5.1 V; 7 V VRESX 37 V; 7 V VSDIAG 37 V; FEN1 = FEN2 = VDD; R_REF = 10 k , ±1 %, 100 PPM; -40 °C T A +95 °C; unless other specified. Table 6. General - DC electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Osc Internal oscillator frequency Tested with 10K, 1%, 100ppm Iref resistor 4.75 - 5.25 MHz VRST1 Internal voltage reset VDD after de-glitch time (tPOR) See Figure 6 VDD level for L9660 to report reset condition -deployment drivers are disabled 4.0 - 4.5 V VRST2 Internal voltage reset VDD with no de-glitch time See Figure 6 Guaranteed by design 2.1 - 3.0 V tPOR POR De-glitch timer Timer for VRST1 5 - 25 µs IDD Input current VDD No squib diagnostics. No deployment. - - 15 mA Resistance measurement diagnostics with no fault condition present. -- 17 Short to –0.3V on SQL; VRCM active - - 35 During deployment - - 15 RIREF_H Resistance threshold IREF - - - 60.0 k RIREF_L -2.0 - - k VIH_RESETB Input voltage threshold RESETB -- - 2.0 V VIL_RESETB -0.8 - - V VHYS_RST - 100 - 300 mV VIH_TEST Input voltage threshold TEST Guaranteed by design - 3.2 - V ITESTPD Input pull-down current TEST - 1.0 - 2.5 mA IAOUT_SHRT AOUT pin current limit AOUT short to ground during squib resistance diagnostics -- 20 mA IRESETPU Input pull-up current RESETB RESETB = VIH to GND -10 - -50 µA IRESx Quiescent current for VRESx during HSS test Current per pin during HSS test excluding selected channel - - 10 µA VIH Input voltage threshold (MOSI, SCLK, CS_D) Input Logic = 1 - - 2.0 V VIL Input Logic = 0 0.8 - - V VHYST Input hysteresis (MOSI, SCLK, CS_D) 100 - 300 mV |
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