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HPC16004 Arkusz danych(PDF) 6 Page - National Semiconductor (TI) |
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HPC16004 Arkusz danych(HTML) 6 Page - National Semiconductor (TI) |
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6 / 36 page ![]() 30 MHz (Continued) AC Electrical Characteristics (See Notes 1 and 4 and Figure 1 through Figure 5 ) VCC 5V g10% unless otherwise specified TA 0 Cto a70 C for HPC4606446004 b40 Cto a85 C for HPC3606436004 b40 Cto a105 C for HPC2606426004 b55 Cto a125 C for HPC1606416004 Symbol and Formula Parameter Min Max Units Notes tDC1ALER Delay from CKI Rising Edge to 035 ns (Notes 1 2) ALE Rising Edge tDC1ALEF Delay from CKI Rising Edge to 035 ns (Notes 1 2) ALE Falling Edge tDC2ALER tC a 20 Delay from CK2 Rising Edge to 37 ns (Note 2) ALE Rising Edge tDC2ALEF tC a 20 Delay from CK2 Falling Edge to 37 ns (Note 2) ALE Falling Edge tLL tC b 9 ALE Pulse Width 24 ns tST tC b 7 Setup of Address Valid before 9ns ALE Falling Edge tVP tC b 5 Hold of Address Valid after 11 ns ALE Falling Edge tARR tC b 5 ALE Falling Edge to RD Falling Edge 11 ns tACC tC a WS b 32 Data Input Valid after Address Output Valid 100 ns (Note 6) tRD tC a WS b 39 Data Input Valid after RD Falling Edge 60 ns tRW tC a WS b 14 RD Pulse Width 85 ns tDR tC b 15 Hold of Data Input Valid after 035 ns RD Rising Edge tRDA tC b 15 Bus Enable after RD Rising Edge 51 ns tARW tC b 5 ALE Falling Edge to WR Falling Edge 28 ns tWW tC a WS b 15 WR Pulse Width 101 ns tV tC a WS b 5 Data Output Valid before WR Rising Edge 94 ns tHW tC b 10 Hold of Data Valid after WR Rising Edge 7 ns tDAR tC a WS b 50 Falling Edge of ALE to 33 ns Falling Edge of RDY tRWP tC RDY Pulse Width 66 ns Note CL 40 pF Note 1 These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall times (tCKIR and tCKIL) on CKI input less than 25 ns Note 2 Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either CKI or CKO is connected to any external logic other than the passive components of the crystal circuit Note 3 tHAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed If HLD falling edge occurs later tHAE may be as long as (3 tC a 4WS a 72 tC a 100) may occur depending on the following CPU instruction cycles its wait states and ready input Note 4 WS (tWAIT) c (number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency tC 30 MHz with one wait state programmed Note 5 Due to emulation restrictionsactual limits will be better Note 6 This is guaranteed by design and not tested 6 |
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