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WM8773 Arkusz danych(PDF) 8 Page - Wolfson Microelectronics plc |
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WM8773 Arkusz danych(HTML) 8 Page - Wolfson Microelectronics plc |
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8 / 29 page ![]() WM8773 Product Preview PP Rev 1.0 June 2002 8 MASTER CLOCK TIMING MCLK t MCLKL t MCLKH t MCLKY Figure 1 Master Clock Timing Requirements Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, AGND, DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information MCLK System clock pulse width high tMCLKH 11 ns MCLK System clock pulse width low tMCLKL 11 ns MCLK System clock cycle time tMCLKY 28 ns MCLK Duty cycle 40:60 60:40 Table 1 Master Clock Timing Requirements DIGITAL AUDIO INTERFACE – MASTER MODE BCLK DOUT ADCLRC WM8773 ADC DSP/ ENCODER/ DECODER Figure 2 Audio Interface - Master Mode |
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