STW81200 datasheet(25/58 Pages) STMICROELECTRONICS

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STW81200

Circuit description

7.3

PLL N divider

The N divider sets the division ratio in the PLL feedback path.

Both Integer-N and Fractional-N PLL architectures are implemented in order to ensure the

best overall performance of the synthesizer.

The Fractional-N division is achieved combining the integer divider section with a Delta-

Sigma modulator (DSM) which sets the fractional part of the overall division ratio.

The DSM is implemented as a MASH structure with programmable order (2 bit; 1st, 2nd, 3rd

and 4th order), programmable MODULUS (21 bit).

It includes also a DITHERING function (1 bit) which can be used to reduce fractional spur

tones by spreading the DSM sequence and consequently the energy of the spurs over a

wider bandwidth.

The overall division ratio N is given by:

The integer part NINT is 17-bit programmable and can range from 24 to 131071 in Integer

Mode. For NINT ≥ 512 the fractional mode is not allowed and the setting used for DSM does

not have any effect.

Based upon the selected order of the Delta-Sigma Modulator the allowed range of NINT

values changes as follows:

•

24 to 510 - 1st Order DSM

•

25 to 509 - 2nd Order DSM

•

27 to 507 - 3rd Order DSM

•

31 to 503 - 4th Order DSM

The fractional part NFRAC of the division ratio is controlled by setting the values FRAC and

MOD (21 bits each) and it depends also on the value of DITHERING (1 bit):

The MOD value can range from 2 to 2097151, while the range of FRAC is from 0 to MOD-1.

If the DITHERING function is not used (DITHERING=0) the fractional part of N is simply

achieved as ratio of FRAC over MOD.

NNINT NFRAC

NFRAC

FRAC

MOD

-----------------

DITHERING

2MOD

⋅

-----------------------------------

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