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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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PC87334VLJ Arkusz danych(PDF) 92 Page - National Semiconductor (TI) |
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PC87334VLJ Arkusz danych(HTML) 92 Page - National Semiconductor (TI) |
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92 / 102 page  100 Electrical Characteristics (Continued) 1036 Receiver Timing Symbol Parameter Conditions Min Max Units tIRRXW IRRX Pulse Width 16 ms 316 Baud Out Cycles tRAI Delay from Active Edge of RD to Reset IRQ 78 ns tRINT Delay from Inactive Edge of RD (RD LSR) to Reset IRQ 55 ns tSCD Delay from RCLK to Sample Time (Note 1) 41 ns tSINT Delay from Stop Bit to Set Interrupt 2 Baud Out Cycles Note 1 This is an internal timing and is therefore not tested TLC12039 – 29 FIGURE 10-6a Receiver Timing TLC12039 – 30 Note 2 If SCR0 e 1 then tSINT e 3 RCLKs For a Timeout interrupt tSINT e 8 RCLKs FIGURE 10-6b FIFO Mode Receiver Timing 92 |
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