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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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USB97CFDC Arkusz danych(PDF) 14 Page - SMSC Corporation |
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USB97CFDC Arkusz danych(HTML) 14 Page - SMSC Corporation |
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14 / 20 page  SMSC DS – USB97CFDC Page 14 Rev. 12/15/2000 FIGURE 4 - SRAM MEMORY READ TIMING Table 5 – SRAM Memory Read Timing NAME PARAMETER MIN TYP MAX UNITS t1 SA[19:0] valid before nMEMRD asserted 10 ns t2 nMEMRD pulse width 100 ns t3 SD[7:0] Data setup time to nMEMRD de-asserted 50 ns t4 SD[7:0] Data hold time from nMEMRD de-asserted 20 ns t5 nMEMRD de-asserted to SA [13:0] invalid 10 ns FIGURE 5 - DISK DRIVE TIMING SA [1 3 :0 S D [7 :0 ] nM E M R t1 t5 t3 t4 t2 TYP t3 t1 t2 t4 t5 t6 t7 t8 nDIR nSTEP nDS0 nINDEX nRDATA nWDATA *X specifies one MCLK period and Y specifies one WCLK period. MCLK = 16x Data Rate (at 500 Kbp/s MCLK = 8 MHz) WCLK = 2x Data Rate (at 500 Kbp/s WCLK = 1 MHz) PARAMETER MIN MAX UNITS t1 t2 t3 t4 t5 t6 t7 t8 nDIR Set Up to nSTEP Low nSTEP Active Time Low nDIR Hold Time After nSTEP nSTEP Cycle Time nDS0-1 Hold Time from nSTEP Low nINDEX Pulse Width nRDATA Active Time Low nWDATA Write Data Width Low X* X* X* X* X* X* ns Y* 4 24 96 132 20 2 40 .5 NAME |
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