Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

AM24LC21 Arkusz danych(PDF) 4 Page - List of Unclassifed Manufacturers

Numer części AM24LC21
Szczegółowy opis  Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM
PDF  13 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  ETC [List of Unclassifed Manufacturers]
Strona internetowa  
Logo ETC - List of Unclassifed Manufacturers

AM24LC21 Arkusz danych(HTML) 4 Page - List of Unclassifed Manufacturers

  AM24LC21 Datasheet HTML 1Page - List of Unclassifed Manufacturers AM24LC21 Datasheet HTML 2Page - List of Unclassifed Manufacturers AM24LC21 Datasheet HTML 3Page - List of Unclassifed Manufacturers AM24LC21 Datasheet HTML 4Page - List of Unclassifed Manufacturers AM24LC21 Datasheet HTML 5Page - List of Unclassifed Manufacturers AM24LC21 Datasheet HTML 6Page - List of Unclassifed Manufacturers AM24LC21 Datasheet HTML 7Page - List of Unclassifed Manufacturers AM24LC21 Datasheet HTML 8Page - List of Unclassifed Manufacturers AM24LC21 Datasheet HTML 9Page - List of Unclassifed Manufacturers Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 13 page
background image
AM24LC21
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM
(Preliminary)
Anachip Corp.
www.anachip.com.tw
Rev 0.0 Aug 10, 2002
4/13
AC Electrical Characteristics
Standard Mode
Vcc=4.5V~5.5V
Fast mode
Symbol
Parameter
Min
Max
Min
Max
Unit
Remarks
FCLK
Clock frequency
100
400
Khz
TH
Clock high time
4
0.6
us
TL
Clock low time
4.7
1.3
us
TR
SDA and SCL rise
time
1
0.3
us
(Note1)
TF
SDA and SCL fall
time
0.3
0.3
us
(Note1)
THD(ST)
Start condition hold
time
4
0.6
us
After this period the first
clock pulse is generated
TSU(ST)
Start
condition
setup time
4.7
0.6
us
Only relevant for
repeated start condition
THD(DI)
Data input hold time
0
0
us
(Note 2)
TSU(DI)
Data
input
setup
time
0.25
0.1
us
TSU(STP)
Stop
condition
setup time
4
0.6
us
TAA
Output valid from
clock
3.5
0.9
us
(Note 2)
TBUF
Bus free time
4.7
1.3
us
Time the bus must be
free before a new
transmission can start
TOF
Output fall time from
VIH(min) to VIL(max)
0.25
20+0.1CB
0.25
us
(Note 1), CB≤100pF
TSP
Input
filter
spike
suppression
(SDA
and SCL pins)
0.05
0.05
us
(Note 3)
TWR
Write cycle time
10
10
ms
Byte or page mode
TVAA
Output valid from
VCLK
2
1
TVH
VCLK high time
4
0.6
TVL
VCLK low time
4.7
1.3
TVHZ
Mode transition time
0.5
0.5
TVPU
Transmit only power
up time
0
0
Endurance
1M
1M
cycles
25
0C, V
CC=5V, Block
mode (Note 4)
Note 1. Not 100% tested. CB=total capacitance of one bus line in pF.
Note 2. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the
falling edge of SCL to avoid unitended generation of start or stop conditions
Note 3. The combined TSP and Vhys specifications are due to new schmitt trigger inputs which provide improved noise and spike
suppression. This eliminates the need for a Tl specification for standard operation.
Note 4. This parameter is not tested but ensured by characterization.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13


Arkusz danych Pobierz

Go To PDF Page


Link URL



Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Link do karty katalogowej    |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com