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TMS320DM6431 Arkusz danych(PDF) 97 Page - Texas Instruments |
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TMS320DM6431 Arkusz danych(HTML) 97 Page - Texas Instruments |
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97 / 227 page ![]() TMS320DM6431 Digital Media Processor www.ti.com SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008 Table 3-33. Serial Port Sub-Block 1 Function Selection PINMUX1.SPBK1 BLOCK FUNCTION RESULTING PIN FUNCTIONS 00 GPIO (6) (default) GPIO: GP[110:105] 01 Reserved – McASP0 Transmit with 1 Serializer and McASP0: AXR0[0], ACLKX0, AFSX0, AHCLKX0, 10 Mute Control AMUTEIN0(1), AMUTE0 11 Reserved – (1) The input from the AMUTEIN0/GP[109] pin is connected to both the McASP0 and GPIO. In addition, the VDD3P3V_PWDN.SP field determines the power state of the Serial Port Block pins. The Serial Port Block pins default to powered down and not operational. To use these pins, user must first program VDD3P3V_PWDN.SP = 0 to power up the pins. For more details on the VDD3P3V_PWDN.SP field, see Section 3.2, Power Considerations. To facilitate McASP0 operation, the input from the AMUTEIN0/GP[109] pin is connected to both the McASP0 and the GPIO module. Therefore when an external mute event occurs, in addition to notifying the McASP0, it can also cause an interrupt through the GPIO module. Submit Documentation Feedback Device Configurations 97 |
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